The present invention relates generally to semiconductor memory devices, and more particularly to synchronous semiconductor memory devices having access to a memory cell array based on an n-bit prefetch mode.
In a synchronous semiconductor memory device it is desirable to operate the device at a high external clock frequency. As a result, the synchronous memory device may have to be capabile of being read from and written to at high speeds. One method of increasing the speed in accessing a synchronous memory device is by using an n-bit prefetch (n is an integer greater than 1) whereby n-bits of data are accessed from the memory array at a first portion of a read operation and then synchronously output from the synchronous memory device on subsequent clock cycles. Examples of a 2-bit prefetch operation in a synchronous semiconductor memory device are disclosed in Japanese Patent Application Laid-Open No. Hei 9-63263 (Semiconductor Memory Device) and Japanese Patent Application Laid-Open No. Hei 11-39871 (Synchronous Type Semiconductor Memory Device).
One such example of a synchronous semiconductor memory device is a Synchronous Dynamic Random Access Memory (SDRAM). To better understand the various aspects of the present invention a conventional 2-bit prefetch operation will be described with respect to a SDRAM. Referring now to FIG. 15, a SDRAM with a conventional 2-bit prefetch operation is set forth. The SDRAM of FIG. 15 includes a Y-address buffer decoder 100, a memory cell array 200, and sense amplifiers (301 (AMP1) and 302 (AMP2)). The memory cell array 200 is divided into memory cell segments (201 and 202) with each memory cell segment (201 and 202) being equal halves of the memory cell array 200.
The Y-address buffer 100 receives a Y-address (column address) signal and an external master clock signal (CLK) from outside the chip or integrated circuit. Based on the value of the Y-address signal, the Y-address buffer decoder 100 activates a column switch line from a group of column switch lines YSW1 corresponding to the memory cell segment 201 and a column switch line from a group of column switch lines YSW2 corresponding to the memory cell segment 202. The column switch line is activated synchronously with the clock signal CLK.
The column switch lines YSW1 and YSW2 designate even column switch lines (YSW1) and odd column switch lines (YSW2). Thus, when the Y-address buffer decoder 100 receives an even Y-address value (Y), the Y-address buffer decoder 100 activates a column switch line, which corresponds to the Y-address value (Y), from the group of column switch lines YSW1. Also, at the same time, the Y-address buffer decoder 100 activates a column switch line, which corresponds to the Y address value (Y+1), from the group of column switch lines YSW2.
However, when the Y-address buffer decoder 100 receives an odd Y-address value (Y), the Y-address buffer decoder 100 activates a column switch line, which corresponds to the Y-address value (Y), from the group of column switch lines YSW2. Also, at the same time, the Y-address buffer decoder 100 activates a column switch line, which corresponds to the Y address value (Y+1), from the group of column switch lines YSW1.
Thus, a memory cell from both memory cell segments (201 and 202) can be simultaneously accessed constituting a 2-bit prefetch. The 2 prefetched bits correspond to bits with consecutive column addresses. The memory cell array 200 is divided into two equal halves where each half corresponds to a memory cell segment (201 or 202). Memory cell segment 201 contains only memory cells that have even column addresses and memory cell segment 202 contains only memory cells that have odd column addresses.
Additionally, an X-address (row address) buffer decoder (not shown) is coupled to the memory cell segments (201 and 202) to activate a row of memory cells in each memory cell segment (201 and 202). For example, a X-address signal is received externally from the SDRAM and used to activate a word line (not shown) in each memory cell segment (201 and 202). Then, based on the Y-address signal (column address) received externally from the SDRAM, a column switch line is selected from each of the groups of column switch lines (YSW1 and YSW2) to access a bit with an even column address from memory cell segment 201 and a bit with an odd column address from memory cell segment 202. These accessed memory cells have a row address which corresponds to the value of the received X-address signal and column addresses which correspond to the value of the received Y-address signal (Y) for one bit and (Y+1) for the other bit.
In the 2-bit prefetch operation, the 2 prefetched bits, which have consecutive column address values, will be simultaneously accessed on I/O buses (RWBS1 and RWBS2) by way of sense amplifiers (301 and 302) and thus a processor can gain access (read/write) to them on successive clock CLK cycles.
Referring now to FIG. 16(a), a timing diagram illustrating the 2-bit prefetch read operation of the SDRAM of FIG. 15 is set forth. In the read operation, a row address signal (not shown) and column address signal (not shown) are applied externally to the SDRAM synchronously with the clock signal CLK having a period of Tclk. The row address signal activates a word line in each memory cell segment (201 and 202). The read operation is a 4-bit burst read with the beginning bit identified by the externally applied row and column address signals. When data in the form of a burst is written to or read from a SDRAM in a prefetch mode, the address values accessed by the column switch lines (YSW1 and YSW2) will differ depending whether a sequential or interleaved count mode is used as designated by an external control signal and the externally applied column address. For simplicity, it is assumed that the SDRAM is operating in the sequential count mode and that the least significant bit of the externally applied column address is a zero. The accessed column addresses A1-A4 are sequential addresses with one bit increment between each.
Given the above conditions address A1 is an even number, thus at time t1 a column switch line from the group of column switch lines YSW1 which corresponds to address A1 is activated. Also at time t1 a column switch line from the group of column switch lines YSW2 which corresponds to address A2 (=A1+1) is activated. DATA1 and DATA2 from memory cell segments 201 and 202 are thus output to I/O buses RWBS1 and RWBS2 respectively after a circuit propagation delay from t1.
Two clock CLK cycles later at time t3 another column switch line from the group of column switch lines YSW1 which corresponds to address A3 (=A1+2) is activated. Also at time t3 a column switch line from the group of column switch lines YSW2 which corresponds to address A4 (=A1+3) is activated. Thus, DATA3 and DATA4 from memory cell segments 201 and 202 are thus output to I/O buses RWBS1 and RWBS2 respectively after a circuit propagation delay from t3.
The data on the I/O buses RWBS1 and RWBS2 (first DATA1 and DATA2 and then DATA3 and DATA4) are alternately latched at a predetermined timing synchronously with the clock signal CLK, and then sequentially output externally as data signals DQ synchronously with and on sequential CLK cycles.
The change of the activation of the column switch lines YSW1 and YSW2 (from A1 to A3 or from A2 to A4) during the burst cycle is performed synchronously with the external clock signal CLK by circuitry within the Y-address buffer decoder 100 and controlled by a control circuit on the SDRAM (not shown).
For the 2-bit prefetch mode as shown in FIG. 16(a) it takes two CLK cycles to access each group of prefetched data onto I/O buses (RWBS1 and RWBS2). However, data signals DQ are output every CLK cycle synchronously with CLK. Thus, the access speed to the individual memory cells occurs at a slower rate (approximately half) than the data is provided externally from the SDRAM. Because of the two clock cycle internal access window, an increase in the external clock signals will increase the data transmission rate.
Referring now to FIG. 16(b), a timing diagram illustrating a conventional non-prefetch read operation (also known as pipeline) of an SDRAM is set forth. It can be seen that both the data on the internal I/O bus RWBUS and the external data signals DQ are transmitted, synchronously with, and in a single CLK cycle. It is noted that the column switch line YSW also switches every CLK cycle.
Referring now to FIG. 17, a timing diagram illustrating the 2-bit prefetch read operation of a DDR-SDRAM (Double Data Rate SDRAM) is set forth. The read operation is a 4-bit burst read with the beginning bit identified by the externally applied row and column address signals (not shown). However, in the DDR-DRAM, the Y-address buffer decoder 100 is configured to allow operations to occur synchronously with both the rising and falling edges of each CLK signal.
For the 2-bit prefetch mode in a DDR-SDRAM as shown in FIG. 17 it takes one CLK cycle to access each group of prefetched data onto I/O buses (RWBS1 and RWBS2). However, data signals DQ are output every half CLK cycle synchronously with the rising and falling edges of CLK. Thus, the access speed to the individual memory cells occurs at a slower rate (approximately half) than the data is provided externally from the SDRAM. This will typically allow for the capability of a faster external clock CLK than in the conventional non-prefetch operation.
For the 2-bit prefetch mode, the case of the DDR-SDRAM illustrated in FIG. 17, is similar to the SDR-SDRAM (Single Data Rate SDRAM) illustrated in FIG. 16(a) in that the 2-bits prefetched in parallel requires a circuit for selecting an additional column switch line (YSW1 and YSW2). However, an SDRAM that does not prefetch the data, as illustrated in FIG. 16(b), does not require the additional column switch line (YSW1 and YSW2), but instead accesses data from the memory cell array 200 at twice the rate, which could be in as little as half the period (Tclk) of the external clock CLK in a DDR-SDRAM.
An SDRAM based on the conventional 2-bit prefetch mode activates two column switch lines (YSW1 and YSW2) simultaneously and will also require two I/O buses to become active at the same time. These requirements mean that a pair of column switch line drivers (not shown) and sense amplifiers (301 and 302) will be active for each data bit. Instances in which increased circuit activation occurs are shown with a xe2x80x9c*xe2x80x9d in FIGS. 16(a) and 17. In the case of a SDRAM that has 16 DQs (xc3x9716), then 32 such data path circuits will be activated which will create on chip noise due to the current spikes on the voltage supply lines and ground lines. Such noise is particularly troublesome on state of the art SDRAMs that use on-chip voltage regulators that have limited current supplying capabilities and/or have relatively narrow (thus resistive) on chip power buses. In order to minimize access times, column circuitry is activated as soon as the memory cell levels have been sufficiently xe2x80x9csensedxe2x80x9d to enable data to reliably be propagated, thus current spikes during this time are undesirable because they will cause improper data transmission or delays. Such noise will be even more troublesome on a SDRAM that operates with a prefetch mode of 4-bits or even more.
In view of the above discussion, it would be desirable to provide a semiconductor memory device, such as an SDRAM that operates on a multi-bit prefetch mode, may have reduced noise when selecting multiple prefetched bits from the memory cell array.
According to the present invention, a semiconductor memory device configured to receive external control signals and external address signals synchronously with an external clock signal and permit data to be written or read synchronously with the external clock signal includes a latch circuit that receives the external clock and generates latch signals synchronously with the external clock signal with each latch signal being generated at a different time interval.
According to one aspect of the present invention, address decoders receiving an internal address signal, generate a column switch signal synchronously with a received latch signal. The semiconductor memory includes a memory array that is divided into memory array segments. Columns in the memory array segments are addressed by the address decoders at different time intervals and synchronously with the latch signals.
According to one aspect of the present invention, an internal I/O bus receives data from each memory array segment. The memory array segments deliver the data in parallel to the internal I/O buses and the data is thereafter delivered sequentially from the semiconductor memory device as an external data signal DQ. The data from the memory array segments is delivered to the internal I/O buses synchronously with the latch signals.
According to another aspect of the invention, a latch circuit receives an external clock signal, an enable signal, and a voltage reference and generates the latch signals therefrom.
According to another aspect of the invention, the latch signals are generated synchronously with respect to the external clock signal.
According to another aspect of the invention, the latch signals are generated at different time intervals.
According to another aspect of the invention, one latch signal is the logical inversion of another latch signal.
According to another aspect of the invention, the latch signals are pulses having a certain pulse width with at least two latch signals generated at different time intervals.
According to another aspect of the invention, the time interval between latch signals is determined by a delay stage in the latch circuit.
According to another aspect of the invention, the maximum time interval between adjacent latch signals is kept less than or substantially equal to the period of the external clock signal when data is written or read synchronously with a first edge of the external clock signal.
According to another aspect of the invention, the maximum time interval between adjacent latch signals is kept less than or substantially equal to one-half period of the external clock signal when data is written or read synchronously with a first and second edge of the external clock signal.